Referring to FIG. 1, a block diagram illustrating a conventional digital signal processing (DSP) operation is shown. A DSP memory 10 can be divided into a number of memory banks 12a-12n. There can also be a number of modules 14a-14n that access the memory 10. Each module 14a-14n has a memory address bus 16a-16n, respectively, that presents addresses for accessing the memory 10. The upper bits of the address busses 16a-16n determine which memory bank 12a-12n a particular one of the modules 14a-14n accesses.
Conventionally, DSP operations occur in a pipeline fashion. The DSP operations are divided into N pipeline stages, with each module 14a-14n working on one pipeline stage at one time. For example, a module 14j accesses a memory bank 12i in one particular time slot and in the next time slot, the module 14j accesses a memory bank 12(i+1) and so on.
Each module 14a-14n (i.e., the software or firmware) needs to keep track of the current time slot and program the memory address (i.e., bank number) accordingly. Keeping track of the current time slot and programming the memory address increases software overhead and can degrade system performance.